发明申请
US20070005677A1 Method and system for multiplier optimization 失效
乘法器优化的方法和系统

Method and system for multiplier optimization
摘要:
Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.
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