发明申请
- 专利标题: Method and system for multiplier optimization
- 专利标题(中): 乘法器优化的方法和系统
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申请号: US11172706申请日: 2005-06-29
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公开(公告)号: US20070005677A1公开(公告)日: 2007-01-04
- 发明人: Chhavi Kishore , Vivek Bhargava , Charles Monahan
- 申请人: Chhavi Kishore , Vivek Bhargava , Charles Monahan
- 主分类号: G06F7/52
- IPC分类号: G06F7/52
摘要:
Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By increasing the number of digits in a multiplication result, partial products within a multiplication can be truncated. When the multiplication result is used in a subsequent operation, the gates required for the increased number of digits in the multiplication result can be made less than the gates saved within the multiply.
公开/授权文献
- US07567998B2 Method and system for multiplier optimization 公开/授权日:2009-07-28
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