发明申请
US20070006115A1 Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device
有权
用于验证掩模图案数据的方法,用于制造掩模的方法,掩模图案验证程序以及用于制造半导体器件的方法
- 专利标题: Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device
- 专利标题(中): 用于验证掩模图案数据的方法,用于制造掩模的方法,掩模图案验证程序以及用于制造半导体器件的方法
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申请号: US11472441申请日: 2006-06-22
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公开(公告)号: US20070006115A1公开(公告)日: 2007-01-04
- 发明人: Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
- 申请人: Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
- 优先权: JP2005-185194 20050624
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a mask used in order to produce the design circuit pattern is prepared. A circuit pattern which is to be obtained by processing a film using the pattern of the mask indicated by the mask pattern data is acquired. Circuit data on a circuit realized by at least a first part of the circuit pattern is produced. A circuit mismatch part where the circuit data and a part of the design circuit data which corresponds to the first part of the circuit pattern do not match up is detected.
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