发明申请
- 专利标题： 0th droop detector architecture and implementation
- 专利标题（中）： 第0个下垂检测器架构和实现
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申请号： US11172250申请日： 2005-06-30
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公开(公告)号： US20070013414A1公开(公告)日： 2007-01-18
- 发明人: Fabrice Paillet , Tanay Karnik , Jianping Xu , Vivek De
- 申请人： Fabrice Paillet , Tanay Karnik , Jianping Xu , Vivek De
- 主分类号： H03K5/00
- IPC分类号： H03K5/00
摘要：
A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.
公开/授权文献
- US07528619B2 0th droop detector architecture and implementation 公开/授权日：2009-05-05
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