An abnormal condition detection circuit, an integrated circuit (IC) card having a central processing unit (CPU), and a method of operating the CPU, allow the CPU to be reset when an abnormal condition is detected in the IC card. The IC card includes the CPU, a non-volatile memory, an abnormal condition detection circuit, and a reset signal generator. The IC card includes detectors that detect a corresponding abnormal condition in the IC card, and an enable signal generation circuit that generates a reset enable signal and an interrupt enable signal in response to an interrupt control signal and a detection signal output from at least one of the detectors. The reset signal generator generates a reset signal in response to the reset enable signal. The CPU is reset in response to the reset signal and interrupted in response to the interrupt enable signal.