The channel regions (T) of the memory cells are directed transversly to the word lines (2), which are arranged parallel at a distance from one another. Local interconnects (6) connect the source/drain regions of the memory cell transistors to bit lines running across the word lines and are connected to local interconnects in every next but one interspace between neighboring word lines. Every local interconnect is connected to only one source/drain region, which is enabled by enlarged shallow trench isolations (7) between the active areas. This memory cell array allows an individual programming and erasing of every single cell and can be integrated with a flash memory array comprising local interconnects and upper bit lines and is intended for file storage.