A switch circuit 1 includes a unit circuit including capacitors 12, 14, an inductor 20, and a FET 30 (switching element). The capacitors 12, 14 are provided in a path P1 (first path) connecting I/O terminals 92, 94. The capacitors 12, 14 are serially connected to each other. To the path P1, a path P2 (second path) is connected. The path P2 includes the inductor 20 and the FET 30, which are serially connected to each other. To be more detailed, an end of the inductor 20 is connected to a connection point N, and the drain (or source) of the FET 30 is connected to the other end of the inductor 20. The source (or drain) of the FET 30 is grounded.