An error correction coding apparatus which improves the throughput of the whole system, while minimizing the increase of the circuit size and the amount of processing operation of the whole apparatus. In this apparatus, a data divider 132 divides transmission data into a plurality of blocks to generate n divided blocks. The n error correction coders out of N error correction coders 134 carry out an error correction coding on each of the n divided blocks in units of block, and outputs the divided blocks. A data concatenator 136 concatenates the n code blocks that have been error-correction-coded in units of block. A division/concatenation controller 138 controls at least one of data divider 132 and data concatenator 136 so that the division of the transmission data and the concatenation of the code blocks are carried out in units of bit.