发明申请
- 专利标题: Methods to facilitate etch uniformity and selectivity
- 专利标题(中): 促进蚀刻均匀性和选择性的方法
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申请号: US11207493申请日: 2005-08-19
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公开(公告)号: US20070042599A1公开(公告)日: 2007-02-22
- 发明人: Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
- 申请人: Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
公开/授权文献
- US07341941B2 Methods to facilitate etch uniformity and selectivity 公开/授权日:2008-03-11