发明申请
US20070050572A1 Output buffer circuit with de-emphasis function 失效
具有去加重功能的输出缓冲电路

  • 专利标题: Output buffer circuit with de-emphasis function
  • 专利标题(中): 具有去加重功能的输出缓冲电路
  • 申请号: US11498084
    申请日: 2006-08-03
  • 公开(公告)号: US20070050572A1
    公开(公告)日: 2007-03-01
  • 发明人: Makoto Tanaka
  • 申请人: Makoto Tanaka
  • 申请人地址: JP Kawasaki
  • 专利权人: NEC ELECTRONICS CORPORATION
  • 当前专利权人: NEC ELECTRONICS CORPORATION
  • 当前专利权人地址: JP Kawasaki
  • 优先权: JP2005-240775 20050823
  • 主分类号: G06F13/00
  • IPC分类号: G06F13/00
Output buffer circuit with de-emphasis function
摘要:
Disclosed is an output buffer circuit including main-data output buffers; a de-emphasis output buffer; and a selector that performs switching control in such a way that, based on a control signal indicating whether de-emphasis is to be enabled or disabled, main data is supplied to the de-emphasis output buffer to make the buffer operate as a main-data output buffer when the control signal indicates that de-emphasis is to be disabled, while emphasis data obtained on delaying the main data by the delay circuit is supplied to the de-emphasis output buffer to make the buffer operate as a de-emphasis output buffer when the control signal indicates that de-emphasis is to be enabled.
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