An apparatus and method to determine the amount of misalignment between a chip carrier and socket by the use of an inspection master. The inspection master is tailored to the perimeter size of the chip carrier and contains alignment marks on the same array as the electrical contact pads of the chip carrier. The inspection master allows bad sockets to be screened out prior to use on a chip carrier and also provides a quantified characterization of the socket array positional error which can be used to adjust the socket fabrication process.