发明申请
US20070072577A1 Single chip GSM/EDGE transceiver architecture with closed loop power control
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单芯片GSM / EDGE收发器架构,具有闭环功率控制
- 专利标题: Single chip GSM/EDGE transceiver architecture with closed loop power control
- 专利标题(中): 单芯片GSM / EDGE收发器架构,具有闭环功率控制
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申请号: US11235907申请日: 2005-09-27
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公开(公告)号: US20070072577A1公开(公告)日: 2007-03-29
- 发明人: Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
- 申请人: Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
- 主分类号: H04B1/28
- IPC分类号: H04B1/28 ; H04M1/00 ; H04B1/44
摘要:
A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.