发明申请
US20070083716A1 Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
有权
链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问
- 专利标题： Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
- 专利标题（中）： 链接高速缓存一致性状态用于对具有出色数据响应的高速缓存行的顺序非均匀访问
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申请号： US11245312申请日： 2005-10-06
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公开(公告)号： US20070083716A1公开(公告)日： 2007-04-12
- 发明人: Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
- 申请人： Ramakrishnan Rajamony , Hazim Shafi , Derek Williams , Kenneth Wright
- 主分类号： G06F13/28
- IPC分类号： G06F13/28
摘要：
A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.
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