Invention Application
US20070083742A1 System and method for time-of-life counter design for handling instruction flushes from a queue
失效
用于处理来自队列的指令刷新的生命周期计数器设计的系统和方法
- Patent Title: System and method for time-of-life counter design for handling instruction flushes from a queue
- Patent Title (中): 用于处理来自队列的指令刷新的生命周期计数器设计的系统和方法
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Application No.: US11246587Application Date: 2005-10-07
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Publication No.: US20070083742A1Publication Date: 2007-04-12
- Inventor: Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Philhower , David Shippy
- Applicant: Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Philhower , David Shippy
- Main IPC: G06F7/38
- IPC: G06F7/38

Abstract:
A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
Public/Granted literature
- US07490224B2 Time-of-life counter design for handling instruction flushes from a queue Public/Granted day:2009-02-10
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