发明申请
- 专利标题: Arithmetic processing unit and method for operating cache
- 专利标题(中): 用于操作缓存的算术处理单元和方法
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申请号: US11510670申请日: 2006-08-28
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公开(公告)号: US20070088896A1公开(公告)日: 2007-04-19
- 发明人: Masahide Kakeda , Masaitsu Nakajima , Takao Yamamoto , Shinji Ozaki
- 申请人: Masahide Kakeda , Masaitsu Nakajima , Takao Yamamoto , Shinji Ozaki
- 优先权: JP2005-303540 20051018
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F13/00
摘要:
A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.