- 专利标题: Net/wiring selection method, net selection method, wiring selection method, and delay improvement method
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申请号: US11637731申请日: 2006-12-13
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公开(公告)号: US20070094625A1公开(公告)日: 2007-04-26
- 发明人: Hiroshi Ikeda
- 申请人: Hiroshi Ikeda
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 优先权: JP2004-168969 20040706
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to include a wiring capacitance lower limit computation step for computing wiring capacitance lower limits on the basis of layout information; an inter-wiring capacitance computation step for computing, as an inter-wiring capacitance, a difference between a real wiring capacitance and the wiring capacitance lower limit; a parallel wiring length extraction step for extracting a parallel wiring length existing between adjacent wirings of the respective wirings; and a selection step for selecting a net/wiring whose layout is to be changed, on the basis of the inter-wiring capacitance, the parallel wiring length, and a slack value.
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