发明申请
US20070103825A1 High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique 有权
采用基板触发和栅极驱动技术的低压器件实现高压ESD电路

High voltage ESD circuit by using low-voltage device with substrate-trigger and gate-driven technique
摘要:
An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.
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