发明申请
- 专利标题: Clock EMI reduction
- 专利标题(中): 时钟EMI降低
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申请号: US11253646申请日: 2005-10-20
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公开(公告)号: US20070103883A1公开(公告)日: 2007-05-10
- 发明人: Sheng Wu , Noah Gottfried , James Burnell , Corey Dayton
- 申请人: Sheng Wu , Noah Gottfried , James Burnell , Corey Dayton
- 专利权人: Fujitsu Network Communications, Inc.
- 当前专利权人: Fujitsu Network Communications, Inc.
- 主分类号: H05K9/00
- IPC分类号: H05K9/00
摘要:
EMI emissions generated by clock signals in a multi-slot electronic system are reduced by providing out-of-phase clock signals to alternate slots, which cause EMI emissions at typical testing distances and farther to be reduced. An electronic equipment comprises a plurality of slots, each slot operable to receive a clock signal and a plurality of phases of the clock signal, wherein a first phase of the clock signal is routed to a portion of the slots and a second phase of the clock signal is routed to a different portion of the slots. The second phase of the clock signal may be substantially 180° out-of-phase with the first phase of the clock signal.
公开/授权文献
- US07519120B2 Clock EMI reduction 公开/授权日:2009-04-14
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