A signal interface for interfacing with an address decoder and a method of address decoding are disclosed. The signal interface comprises: a signal capture element operable to receive an address portion signal associated with a read access to a memory and to provide a first interim address portion signal and a second interim address portion signal, the signal capture element being operable during a pre-charged period to provide a first pre-charged logic level as the first interim address portion signal and the first pre-charged logic level as the second interim address portion signal, the signal capture element being further operable during an evaluate period to output an address portion logic level representative of the address portion signal as the first interim address portion signal and an inverted address portion logic level representative of an inverted address portion signal as the second interim address portion signal; and an inverter circuit operable to receive the first interim address portion signal and the second interim address portion signal from which a first address portion signal and a second address portion signal is respectively derived, the inverter circuit being operable during the pre-charged period to output to an address decoder a second pre-charged logic level as the first address portion signal and the second pre-charged logic level as the second address portion signal, the receipt of the first address portion signal and the second address portion signal at the second pre-charged logic level causing the address decoder to be prevented from causing a data access to the memory from occurring, the inverter circuit having transfer characteristics which cause the first address portion signal and the second address portion signal to be maintained at voltage levels interpreted by the address decoder as being the second pre-charged logic level should the first interim address portion signal or the second interim address portion signal fail to transition to a valid logic level during the evaluate period. By maintaining the address portion signals in this way prevents the address decoder from selecting multiple word lines which ensures no corruption in the state stored in the memory can result due to the inadvertent flow of charge between cells in different rows of the memory even when metastable signals occur during the read access.