发明申请
US20070106967A1 Layout analysis method and apparatus for semiconductor integrated circuit 有权
半导体集成电路布局分析方法和装置

Layout analysis method and apparatus for semiconductor integrated circuit
摘要:
A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.
信息查询
0/0