发明申请
- 专利标题: Layout analysis method and apparatus for semiconductor integrated circuit
- 专利标题(中): 半导体集成电路布局分析方法和装置
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申请号: US11396660申请日: 2006-04-04
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公开(公告)号: US20070106967A1公开(公告)日: 2007-05-10
- 发明人: Yoshio Inoue , Takashi Yoneda , Masaru Ito
- 申请人: Yoshio Inoue , Takashi Yoneda , Masaru Ito
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 优先权: JP2005-323807 20051108
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.
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