发明申请
US20070117338A1 Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same
失效
通过阵列电容器，并入通孔阵列电容器的布线板及其制造方法
- 专利标题： Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same
- 专利标题（中）： 通过阵列电容器，并入通孔阵列电容器的布线板及其制造方法
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申请号： US11603161申请日： 2006-11-22
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公开(公告)号： US20070117338A1公开(公告)日： 2007-05-24
- 发明人: Hiroshi Yamamoto , Toshitake Seki , Jun Otsuka , Manabu Sato , Masahiko Okuyama
- 申请人： Hiroshi Yamamoto , Toshitake Seki , Jun Otsuka , Manabu Sato , Masahiko Okuyama
- 专利权人： NGK SPARK PLUG CO., LTD.
- 当前专利权人： NGK SPARK PLUG CO., LTD.
- 优先权： JPP2005-337969 20051124; JPP2006-032984 20060209; JPP2006-281379 20061016
- 主分类号： H01L21/20
- IPC分类号： H01L21/20 ; H01L29/00
摘要：
A via array capacitor comprising: a capacitor body including a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total of a thickness of the metal-containing layers disposed on the first main surface and a thickness of the metal-containing layers disposed on the second main surface is from 15% to 80% of an overall thickness of the via array capacitor.