- 专利标题: Method for fabricating a chip scale package using wafer level processing
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申请号: US11711420申请日: 2007-02-26
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公开(公告)号: US20070148918A1公开(公告)日: 2007-06-28
- 发明人: Larry Kinsman , Salman Akram
- 申请人: Larry Kinsman , Salman Akram
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
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