A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.