A multiprocessor system includes a plurality of masters, at least one first type of slave operating with a first clock frequency, and at least one second type of slave operating with a second clock frequency higher than the first clock frequency. An arbitrator coordinates access between the masters and the slaves via a single read/write bus path between the arbitrator and the first type of slave, and via a plurality of read bus paths and/or a plurality of write bus paths between the arbitrator and the second type of slave.