发明申请
US20070157062A1 Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices
失效
通过扫描子矩阵实现LDPC(低密度奇偶校验)解码器
- 专利标题: Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices
- 专利标题(中): 通过扫描子矩阵实现LDPC(低密度奇偶校验)解码器
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申请号: US11360268申请日: 2006-02-23
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公开(公告)号: US20070157062A1公开(公告)日: 2007-07-05
- 发明人: Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
- 申请人: Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
- 申请人地址: US CA Irvine
- 专利权人: Broadcom Corporation, a California Corporation
- 当前专利权人: Broadcom Corporation, a California Corporation
- 当前专利权人地址: US CA Irvine
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).
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