发明申请
US20070180269A1 I/O address translation blocking in a secure system during power-on-reset
审中-公开
上电复位期间安全系统中的I / O地址转换阻塞
- 专利标题： I/O address translation blocking in a secure system during power-on-reset
- 专利标题（中）： 上电复位期间安全系统中的I / O地址转换阻塞
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申请号： US11344901申请日： 2006-02-01
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公开(公告)号： US20070180269A1公开(公告)日： 2007-08-02
- 发明人: John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
- 申请人： John Irish , Charles Johns , Chad McBride , Ibrahim Ouda , Andrew Wottreng
- 申请人地址： US NY ARMONK
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY ARMONK
- 主分类号： G06F12/14
- IPC分类号： G06F12/14
摘要：
A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.
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