A co-planar thin film transistor, TFT (22), and a method of fabricating the same, in which an additional insulating layer is provided on the source contact (30) and the drain contact (32) and defined such that a first region (34) of the additional insulating layer occupies substantially the same area as the source contact (30) and a second region (36) of the additional insulating layer occupies substantially the same area as the drain contact (32). This tends to provide a reduction in the gate (62) to source capacitance, and the gate (62) to drain capacitance. In some geometries this can be achieved without any additional masks or defining steps.