A TFT array panel having signal lines of low resistivity is presented. The TFT array panel includes a substrate; a gate line including a gate electrode formed on the substrate and having a single-layered structure; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a barrier layer formed on the semiconductor layer and including nitrogen; a data line including a source electrode formed on the barrier layer and having a single-layered structure; a drain electrode formed on the barrier layer, spaced apart from the source electrode and having a single-layered structure; and a pixel electrode electrically connected to the drain electrode. The TFT array panel may include contact holes extending to the end portions of the gate line, the data line, and the drain electrode, and molybdenum or molybdenum alloy buffer members in the contact holes.