发明申请
- 专利标题： Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device
- 专利标题（中）： 终端电阻调节方法，半导体集成电路和半导体器件
-
申请号： US11485396申请日： 2006-07-13
-
公开(公告)号： US20070216441A1公开(公告)日： 2007-09-20
- 发明人: Yutaka Nemoto , Yoshimasa Ogawa , Miki Yanagawa , Makoto Koga
- 申请人： Yutaka Nemoto , Yoshimasa Ogawa , Miki Yanagawa , Makoto Koga
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 优先权： JP2006-076776 20060320
- 主分类号： H03K19/003
- IPC分类号： H03K19/003
摘要：
A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one of a power supply voltage and a ground voltage, controlling a monitoring resistor part which has a plurality of first resistors when making a calibration, so as to selectively couple the first resistors in parallel between the first node and a second voltage based on the comparison result, the second voltage being the other of the power supply voltage and the ground voltage, and controlling a terminating resistor part which has a plurality of second resistors when controlling the terminating resistance of the terminating part, so as to selectively couple the second resistors in parallel between a second node and the second voltage based on the comparison result similarly to the first resistors of the monitoring resistor part.