发明申请
- 专利标题: Reduced pattern memory in digital test equipment
- 专利标题(中): 减少数字测试设备中的模式记忆
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申请号: US11391009申请日: 2006-03-28
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公开(公告)号: US20070234145A1公开(公告)日: 2007-10-04
- 发明人: Daniel Baker , J. White , Ciro Nishiguchi
- 申请人: Daniel Baker , J. White , Ciro Nishiguchi
- 专利权人: National Instruments Corporation
- 当前专利权人: National Instruments Corporation
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing configuration sets. Each selection code indicates an association between a test vector and a configuration set. Each configuration set may be associated with one or more of the test vectors. The configuration sets include information for configuring the interface circuits during communications between the test system and the DUT for each test vector. Each configuration set in the third memory is unique with respect to the other configuration sets, and the number of configuration sets may be less than the number of test vectors.
公开/授权文献
- US07434124B2 Reduced pattern memory in digital test equipment 公开/授权日:2008-10-07