Invention Application
US20070236232A1 SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP
审中-公开
在制造芯片期间使用芯片内部的测试结构的系统和装置
- Patent Title: SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP
- Patent Title (中): 在制造芯片期间使用芯片内部的测试结构的系统和装置
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Application No.: US11763001Application Date: 2007-06-14
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Publication No.: US20070236232A1Publication Date: 2007-10-11
- Inventor: Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
- Applicant: Majid Aghababazadeh , Jose Estabil , Nader Pakdaman , Gary Steinbrueck , James Vickers
- Main IPC: G01R31/305
- IPC: G01R31/305

Abstract:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.
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