- 专利标题: Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide
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申请号: US11498672申请日: 2006-08-02
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公开(公告)号: US20070247915A1公开(公告)日: 2007-10-25
- 发明人: Alexander Kalnitsky , Michael Church
- 申请人: Alexander Kalnitsky , Michael Church
- 申请人地址: US CA Milpitas
- 专利权人: Intersil Americas Inc.
- 当前专利权人: Intersil Americas Inc.
- 当前专利权人地址: US CA Milpitas
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; G11C11/34
摘要:
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
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