发明申请
- 专利标题: Method for fabricating semiconductor package free of substrate
- 专利标题(中): 制造不含衬底的半导体封装的方法
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申请号: US11821269申请日: 2007-06-22
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公开(公告)号: US20070249101A1公开(公告)日: 2007-10-25
- 发明人: Chien Huang , Yu-Po Wang , Chih-Ming Huang
- 申请人: Chien Huang , Yu-Po Wang , Chih-Ming Huang
- 申请人地址: TW Taichung
- 专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人地址: TW Taichung
- 优先权: TW092101197 20030121
- 主分类号: H01L21/60
- IPC分类号: H01L21/60
摘要:
A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.