发明申请
US20070253263A1 Nonvolatile memory device with test mechanism 有权
具有测试机制的非易失性存储器件

  • 专利标题: Nonvolatile memory device with test mechanism
  • 专利标题(中): 具有测试机制的非易失性存储器件
  • 申请号: US11413987
    申请日: 2006-04-28
  • 公开(公告)号: US20070253263A1
    公开(公告)日: 2007-11-01
  • 发明人: Kenji Noda
  • 申请人: Kenji Noda
  • 专利权人: NSCore Inc.
  • 当前专利权人: NSCore Inc.
  • 主分类号: G11C29/00
  • IPC分类号: G11C29/00
Nonvolatile memory device with test mechanism
摘要:
A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.
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