发明申请
- 专利标题： METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
- 专利标题（中）： 减少场效应晶体管重叠电容的方法
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申请号： US11741034申请日： 2007-04-27
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公开(公告)号： US20070254443A1公开(公告)日： 2007-11-01
- 发明人: Huilong Zhu , Oleg Gluschenkov
- 申请人： Huilong Zhu , Oleg Gluschenkov
- 申请人地址： US NY Armonk 10504
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk 10504
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.