发明申请
- 专利标题： Methods for Forming Resistors Including Multiple Layers for Integrated Circuit Devices
- 专利标题（中）： 形成用于集成电路器件的多层电阻器的方法
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申请号： US11780026申请日： 2007-07-19
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公开(公告)号： US20070259494A1公开(公告)日： 2007-11-08
- 发明人: Je-Min Park , Yoo-Sang Hwang
- 申请人： Je-Min Park , Yoo-Sang Hwang
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 优先权： KR2003-75750 20031029
- 主分类号： H01L21/8234
- IPC分类号： H01L21/8234 ; H01L21/4763
摘要：
Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.
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