发明申请
US20070263723A1 DIGITAL SIGNAL CODING APPARATUS, DIGITAL SIGNAL DECODING APPARATUS, DIGITAL SIGNAL ARITHMETIC CODING METHOD AND DIGITAL SIGNAL ARITHMETIC DECODING METHOD
有权
数字信号编码装置，数字信号解码装置，数字信号算术编码方法和数字信号算术解码方法
- 专利标题： DIGITAL SIGNAL CODING APPARATUS, DIGITAL SIGNAL DECODING APPARATUS, DIGITAL SIGNAL ARITHMETIC CODING METHOD AND DIGITAL SIGNAL ARITHMETIC DECODING METHOD
- 专利标题（中）： 数字信号编码装置，数字信号解码装置，数字信号算术编码方法和数字信号算术解码方法
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申请号： US11781682申请日： 2007-07-23
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公开(公告)号： US20070263723A1公开(公告)日： 2007-11-15
- 发明人: Shunichi SEKIGUCHI , Yoshihisa Yamada , Kohtaro Asai
- 申请人： Shunichi SEKIGUCHI , Yoshihisa Yamada , Kohtaro Asai
- 优先权： JP2002-124114 20020425
- 主分类号： H04N7/12
- IPC分类号： H04N7/12
摘要：
In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.
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