The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.