发明申请
US20070281489A1 METHODS FOR MINIMIZING MASK UNDERCUTS AND NOTCHES FOR PLASMA PROCESSING SYSTEM
有权
用于最小化等离子体处理系统的掩模和凹槽的方法
- 专利标题: METHODS FOR MINIMIZING MASK UNDERCUTS AND NOTCHES FOR PLASMA PROCESSING SYSTEM
- 专利标题(中): 用于最小化等离子体处理系统的掩模和凹槽的方法
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申请号: US11421000申请日: 2006-05-30
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公开(公告)号: US20070281489A1公开(公告)日: 2007-12-06
- 发明人: Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
- 申请人: Tamarak Pandhumsoporn , Alferd Cofer , William Bosch
- 主分类号: H01L21/302
- IPC分类号: H01L21/302 ; H01L21/461
摘要:
A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.
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