A multi-CPU computer which is capable of positively performing error handling, and restarting a system even when a fatal error has occurred in a CPU. When a hardware error has occurred in a first CPU, error information is notified to a second CPU by a first error notification circuit of the first CPU. Then, the error information notified from the first CPU is obtained by a second error notification circuit of the second CPU, and error handling based on the error information is requested of an operating system. The second CPU executes a process for storing fault information including the error information in a storage device and a process for restarting the system, according to the operating system.