Invention Application
US20080012133A1 Reducing resistivity in interconnect structures by forming an inter-layer
有权
通过形成一个层间来降低互连结构中的电阻率
- Patent Title: Reducing resistivity in interconnect structures by forming an inter-layer
- Patent Title (中): 通过形成一个层间来降低互连结构中的电阻率
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Application No.: US11486893Application Date: 2006-07-13
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Publication No.: US20080012133A1Publication Date: 2008-01-17
- Inventor: Chih-Chao Shih , Cheng-Lin Huang , Ching-Hua Hsieh , Shau-Lin Shue
- Applicant: Chih-Chao Shih , Cheng-Lin Huang , Ching-Hua Hsieh , Shau-Lin Shue
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.
Public/Granted literature
- US07612451B2 Reducing resistivity in interconnect structures by forming an inter-layer Public/Granted day:2009-11-03
Information query
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