发明申请
- 专利标题： Master-Slave Flip-Flop, Trigger Flip-Flop and Counter
- 专利标题（中）： 主从触发器，触发器触发器和计数器
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申请号： US10572446申请日： 2005-08-09
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公开(公告)号： US20080012619A1公开(公告)日： 2008-01-17
- 发明人: Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
- 申请人： Hiroki Morimura , Satoshi Shigematsu , Yukio Okazaki , Katsuyuki Machida
- 优先权： JP2004-233223 20040810
- 国际申请： PCT/JP04/14579 WO 20050809
- 主分类号： H03K3/3562
- IPC分类号： H03K3/3562
摘要：
A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.
公开/授权文献
- US07440534B2 Master-slave flip-flop, trigger flip-flop and counter 公开/授权日：2008-10-21
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