发明申请
- 专利标题: METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE
- 专利标题(中): 制备双重结构的方法
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申请号: US11458689申请日: 2006-07-20
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公开(公告)号: US20080020581A1公开(公告)日: 2008-01-24
- 发明人: An-Chi Liu
- 申请人: An-Chi Liu
- 主分类号: H01L21/461
- IPC分类号: H01L21/461 ; H01L21/302
摘要:
A semiconductor wafer includes a substrate, a conductive layer, a dielectric layer having a via, a hard mask defined a trench pattern, and a sacrificial layer. Then a sequential of etching processes is performed upon the semiconductor wafer in a chamber to form a trench and expose the conductive layer. By operating all procedures within one chamber, manufacturing time is efficiently shortened and yield is thus increased.
公开/授权文献
- US07884026B2 Method of fabricating dual damascene structure 公开/授权日:2011-02-08
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