发明申请
US20080031064A1 Self-feedback control pipeline architecture for memory read path applications
有权
用于存储器读路径应用的自反馈控制流水线架构
- 专利标题: Self-feedback control pipeline architecture for memory read path applications
- 专利标题(中): 用于存储器读路径应用的自反馈控制流水线架构
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申请号: US11492600申请日: 2006-07-25
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公开(公告)号: US20080031064A1公开(公告)日: 2008-02-07
- 发明人: Ming Hung Wang , Jeng-Tzong Shih
- 申请人: Ming Hung Wang , Jeng-Tzong Shih
- 专利权人: Etron Technology, Inc.
- 当前专利权人: Etron Technology, Inc.
- 主分类号: G11C7/02
- IPC分类号: G11C7/02
摘要:
A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.
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