发明申请
- 专利标题: Trench isolation methods of semiconductor device
- 专利标题(中): 半导体器件的沟槽隔离方法
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申请号: US11973044申请日: 2007-10-05
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公开(公告)号: US20080032483A1公开(公告)日: 2008-02-07
- 发明人: Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
- 申请人: Hyuk-Ju Ryu , Heon-Jong Shin , Hee-Sung Kang , Choong-Ryul Ryou , Mu-Kyeng Jung , Kyung-Soo Kim
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 优先权: KR10-2005-0014241 20050221
- 主分类号: H01L21/78
- IPC分类号: H01L21/78
摘要:
In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.