发明申请
US20080036017A1 METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE
审中-公开
在晶体闸门结构上使用耐蚀衬层以达到高设备性能的方法和结构
- 专利标题： METHOD AND STRUCTURE TO USE AN ETCH RESISTANT LINER ON TRANSISTOR GATE STRUCTURE TO ACHIEVE HIGH DEVICE PERFORMANCE
- 专利标题（中）： 在晶体闸门结构上使用耐蚀衬层以达到高设备性能的方法和结构
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申请号： US11836193申请日： 2007-08-09
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公开(公告)号： US20080036017A1公开(公告)日： 2008-02-14
- 发明人: Hung Ng , Haining Yang
- 申请人： Hung Ng , Haining Yang
- 主分类号： H01L31/00
- IPC分类号： H01L31/00
摘要：
A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.
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