发明申请
- 专利标题: Electrostatic discharge protection circuit and terminating resistor circuit
- 专利标题(中): 静电放电保护电路和终端电阻电路
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申请号: US11819579申请日: 2007-06-28
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公开(公告)号: US20080042686A1公开(公告)日: 2008-02-21
- 发明人: Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Tsuneo Ito , Yuko Tanba
- 申请人: Kanji Otsuka , Tamotsu Usami , Yutaka Akiyama , Tsuneo Ito , Yuko Tanba
- 专利权人: Kanji OTSUKA,Tamotsu USAMI,Yutaka AKIYAMA,Tsuneo ITO,Yuko TANBA,FUJITSU LIMITED,Oki Electric Industry Co., Ltd.,KYOCERA Corporation,Kabushiki Kaisha Toshiba,Fuji Xerox Co., Ltd.,Renesas Technology Corp.
- 当前专利权人: Kanji OTSUKA,Tamotsu USAMI,Yutaka AKIYAMA,Tsuneo ITO,Yuko TANBA,FUJITSU LIMITED,Oki Electric Industry Co., Ltd.,KYOCERA Corporation,Kabushiki Kaisha Toshiba,Fuji Xerox Co., Ltd.,Renesas Technology Corp.
- 优先权: JP2006-177842 20060628
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; H02H9/04
摘要:
Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.
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