发明申请
- 专利标题： SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
- 专利标题（中）： 用于锁定抑制的半导体结构和形成这种半导体结构的方法
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申请号： US11927135申请日： 2007-10-29
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公开(公告)号： US20080057671A1公开(公告)日： 2008-03-06
- 发明人: Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
- 申请人： Toshiharu Furukawa , Robert Gauthier , David Horak , Charles Koburger , Jack Mandelman , William Tonti
- 申请人地址： US NY Armonk 10504
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk 10504
- 主分类号： H01L21/762
- IPC分类号： H01L21/762
摘要：
Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.