发明申请
- 专利标题: METHOD OF FORMING BIT LINE OF SEMICONDUCTOR MEMORY DEVICE
- 专利标题(中): 形成半导体存储器件位线的方法
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申请号: US11680500申请日: 2007-02-28
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公开(公告)号: US20080057688A1公开(公告)日: 2008-03-06
- 发明人: Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
- 申请人: Cheol Mo JEONG , Whee Won Cho , Jung Geun Kim , Seung Hee Hong
- 申请人地址: KR Icheon-si
- 专利权人: Hynix Semiconductor Inc.
- 当前专利权人: Hynix Semiconductor Inc.
- 当前专利权人地址: KR Icheon-si
- 优先权: KR2006-85747 20060906
- 主分类号: H01L21/3205
- IPC分类号: H01L21/3205
摘要:
A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.
公开/授权文献
- US07462536B2 Method of forming bit line of semiconductor memory device 公开/授权日:2008-12-09
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