A chip-scale packaging leadframe for a memory chip is provided, where the external leads of at least a pair of the VDD leads and at least a pair of the VSS leads are arranged on two parallel and opposing sides, namely, the first side and the third side, respectively, while all or almost all external leads of the other leads are arranged on the other two parallel and opposing sides, namely, the second side and the fourth side, respectively. According to the present invention, the dimension of the external leads of the VDD and VSS leads should be at least 0.4×1.15 mm; or the area of the external leads of the VDD and VSS leads should be at least 1.8 times of that of the other leads. Also according to the present invention, the gap of the external leads of adjacent VDD and VSS leads should be at least 1.0 mm; or at least two times of that of the other leads.