Invention Application
- Patent Title: Wafer level chip package and a method of fabricating thereof
- Patent Title (中): 晶圆级芯片封装及其制造方法
-
Application No.: US11522885Application Date: 2006-09-18
-
Publication No.: US20080067663A1Publication Date: 2008-03-20
- Inventor: Teck-Gyu Kang , Belgacem Haba , Guilian Gao
- Applicant: Teck-Gyu Kang , Belgacem Haba , Guilian Gao
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00
Abstract:
Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.
Public/Granted literature
- US08133808B2 Wafer level chip package and a method of fabricating thereof Public/Granted day:2012-03-13
Information query
IPC分类:
